`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/09 00:11:05
// Design Name: 
// Module Name: sim1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim1(

    );
    reg clk, rstb;
    reg [9:0] addr_a = 0, addr_b = 0;
    reg [31:0] data_a = 0, data_b = 0;

    Simple_Dual_Port_RAM RAM(
    .clka(clk),
    .wea(1),
    .addra(addr_a),
    .dina(data_a),
    .clkb(clk),
    .rstb(rstb),
    .addrb(addr_b),
    .doutb(data_b),
    .rsta_busy(),
    .rstb_busy()
    );

    initial begin
        clk = 0; rstb = 1; #20 rstb = 0;
    end


endmodule
